diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index 54470457a..a26ed7ed6 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c
@@ -158,20 +158,21 @@ exit:
 		 * Update the timestamp with cache off.  We assume this
 		 * timestamp can only be read from the current CPU and the
 		 * timestamp cache line will be flushed before return to
 		 * normal world on wakeup.
 		 */
 		PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
 		    RT_INSTR_ENTER_HW_LOW_PWR,
 		    PMF_NO_CACHE_MAINT);
 #endif
 
+		NOTICE("DIE %lx\n", read_mpidr() & 0xf);
 		if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi != NULL) {
 			/* This function must not return */
 			psci_plat_pm_ops->pwr_domain_pwr_down_wfi(&state_info);
 		} else {
 			/*
 			 * Enter a wfi loop which will allow the power
 			 * controller to physically power down this cpu.
 			 */
 			psci_power_down_wfi();
 		}
diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c
index 658529092..0dc6c6d60 100644
--- a/plat/allwinner/common/sunxi_bl31_setup.c
+++ b/plat/allwinner/common/sunxi_bl31_setup.c
@@ -77,20 +77,24 @@ static void *sunxi_find_dtb(void)
 
 	return NULL;
 }
 
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				u_register_t arg2, u_register_t arg3)
 {
 	/* Initialize the debug console as soon as possible */
 	console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ,
 			       SUNXI_UART0_BAUDRATE, &console);
+	console_set_scope(&console,
+			  CONSOLE_FLAG_BOOT |
+			  CONSOLE_FLAG_RUNTIME |
+			  CONSOLE_FLAG_CRASH);
 
 #ifdef BL32_BASE
 	/* Populate entry point information for BL32 */
 	SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
 	bl32_image_ep_info.pc = BL32_BASE;
 #endif
 
 	/* Populate entry point information for BL33 */
 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
@@ -186,20 +190,30 @@ void bl31_platform_setup(void)
 	}
 
 	/* Configure the interrupt controller */
 	gicv2_driver_init(&sunxi_gic_data);
 	gicv2_distif_init();
 	gicv2_pcpu_distif_init();
 	gicv2_cpuif_enable();
 
 	sunxi_security_setup();
 
+	//mmio_write_32(0x70005c0, 0x20000);
+	//mmio_write_32(0x70005c4, 0xfa50392f);
+
+	for (uint32_t i = 0x7000400; i < 0x7000800; i += 16)
+		NOTICE("%08x: %08x %08x %08x %08x\n", i,
+			mmio_read_32(i),
+			mmio_read_32(i + 4),
+			mmio_read_32(i + 8),
+			mmio_read_32(i + 12));
+
 	/*
 	 * On the A64 U-Boot's SPL sets the bus clocks to some conservative
 	 * values, to work around FEL mode instabilities with SRAM C accesses.
 	 * FEL mode is gone when we reach ATF, so bring the AHB1 bus
 	 * (the "main" bus) clock frequency back to the recommended 200MHz,
 	 * for improved performance.
 	 */
 	if (soc_id == SUNXI_SOC_A64)
 		mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180);
 
diff --git a/plat/allwinner/sun50i_h616/sunxi_power.c b/plat/allwinner/sun50i_h616/sunxi_power.c
index 320ba38fd..884c6e6c3 100644
--- a/plat/allwinner/sun50i_h616/sunxi_power.c
+++ b/plat/allwinner/sun50i_h616/sunxi_power.c
@@ -104,27 +104,30 @@ void sunxi_power_down(void)
 		axp_power_off();
 		break;
 	default:
 		break;
 	}
 }
 
 void sunxi_cpu_power_off_self(void)
 {
 	u_register_t mpidr = read_mpidr();
-	unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
-	unsigned int core    = MPIDR_AFFLVL0_VAL(mpidr);
-
-	/*
-	 * According to the Cortex-A53 TRM the core needs to be in WFI state
-	 * before the reset line can be asserted, and the power be removed.
-	 * This sequence can't be observed if we have only this very core
-	 * to perform it.
-	 * So we do as good as we can, we remove the power, then go into
-	 * WFI (should we survive this).
-	 * The CPU_ON sequence does a proper reset from another core, before
-	 * handing this core back to the caller, so that should be fine.
-	 */
-	mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xffU);
-	while (1)
-		wfi();
+	unsigned int core  = MPIDR_AFFLVL0_VAL(mpidr);
+
+	NOTICE("Power down %d\n", core);
+#define CPUIDLE_EN_REG		0x100
+#define CORE_CLOSE_REG		0x104
+#define PWR_SW_DELAY_REG	0x140
+#define CONFIG_DELAY_REG	0x144
+	mmio_write_32(SUNXI_R_CPUCFG_BASE + PWR_SW_DELAY_REG, 24);
+	mmio_write_32(SUNXI_R_CPUCFG_BASE + CONFIG_DELAY_REG, 24);
+	mmio_write_32(SUNXI_R_CPUCFG_BASE + CPUIDLE_EN_REG, 0x16aa0000);
+	mmio_write_32(SUNXI_R_CPUCFG_BASE + CPUIDLE_EN_REG, 0xaa160001);
+	mmio_write_32(SUNXI_R_CPUCFG_BASE + CORE_CLOSE_REG, BIT_32(core));
+
+	for (uint32_t i = 0x7000400; i < 0x7000600; i += 16)
+		NOTICE("%08x: %08x %08x %08x %08x\n", i,
+			mmio_read_32(i),
+			mmio_read_32(i + 4),
+			mmio_read_32(i + 8),
+			mmio_read_32(i + 12));
 }