From 4b77cb89c084f904cb3fdb6e7acb6bb652d9c721 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 17 Oct 2022 12:26:27 +0200 Subject: [PATCH] ASoC: cs42l84: Enable regcache (initially) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin PoviĊĦer --- sound/soc/codecs/cs42l84.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/cs42l84.c b/sound/soc/codecs/cs42l84.c index f95e0e5153c7..b0c5bdec38fc 100644 --- a/sound/soc/codecs/cs42l84.c +++ b/sound/soc/codecs/cs42l84.c @@ -56,12 +56,35 @@ struct cs42l84_private { int hs_type; }; +static const struct reg_default cs42l84_reg_defaults[] = { +}; + +bool cs42l84_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS42L84_DEVID ... CS42L84_DEVID+5: + case CS42L84_TSRS_PLUG_INT_STATUS: + case CS42L84_PLL_LOCK_STATUS: + case CS42L84_TSRS_PLUG_STATUS: + case CS42L84_HS_DET_STATUS2: + return true; + default: + return false; + } +} + static const struct regmap_config cs42l84_regmap = { .reg_bits = 16, .val_bits = 8, + .volatile_reg = cs42l84_volatile_register, + .max_register = 0xffff, - .cache_type = REGCACHE_NONE, + /* + .reg_defaults = cs42l84_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(cs42l84_reg_defaults), + */ + .cache_type = REGCACHE_RBTREE, .use_single_read = true, .use_single_write = true, -- 2.37.0 (Apple Git-136)