[cpu0] Pass: mrs x19, L2C_ERR_STS_EL1 = 0 (L2C_ERR_STS_EL1) [cpu0] Pass: mrs x1, L2C_ERR_ADR_EL1 = 0 (L2C_ERR_ADR_EL1) [cpu0] Pass: mrs x1, L2C_ERR_INF_EL1 = 0 (L2C_ERR_INF_EL1) [cpu0] Pass: msr L2C_ERR_STS_EL1, x19 = 0 (OK) (L2C_ERR_STS_EL1) [cpu0] Pass: mrs x1, E_LSU_ERR_STS_EL1 = 0 (E_LSU_ERR_STS_EL1) [cpu0] Pass: mrs x1, E_FED_ERR_STS_EL1 = 0 (E_FED_ERR_STS_EL1) [cpu0] Pass: mrs x1, E_MMU_ERR_STS_EL1 = 0 (E_MMU_ERR_STS_EL1) [cpu0] Pass: mrs x8, L2C_ERR_STS_EL1 = 0 (L2C_ERR_STS_EL1) [cpu0] Pass: msr L2C_ERR_STS_EL1, x8 = 0 (OK) (L2C_ERR_STS_EL1) [cpu0] Guest exception: EXCEPTION_LOWER/SYNC == Exception taken from EL1h == SPSR = 0x800003c5 (N=1, Z=0, C=0, V=0, TCO=0, DIT=0, UAO=0, PAN=0, SS=0, IL=0, SSBS=0, BTYPE=0, D=1, A=1, I=1, F=1, M=0x5(EL1h)) ELR = 0x1001ee4090c (0x1001ee4090c) SP_EL1 = 0x1001ef13d90 (0x1001ef13d90) ESR = 0x5a000000 (ISS2=0x0, EC=0x16(HVC), IL=1, ISS=0x0) FAR = 0x39b200020 (0x39b200020) x0-x3 = 0000000000000004 000001001ef13b82 0000000000000000 000001001ef13b40 x4-x7 = 0000000000000010 0000000000000000 00000000ffffffff 0000000000000000 x8-x11 = 0000000000000000 0000000000000000 000000039b200000 000000000000000a x12-x15 = 0000000000000000 0000000000000001 00000000ffffffff 000001001ee74d86 x16-x19 = 0000000000000000 0000000000000022 00000000ffffffff 0000000000000000 x20-x23 = 000001001ef13de0 000001002e4290a0 000001001eee8040 0000000000000000 x24-x27 = 0000000000000005 0000000000000000 000000000e3a1674 0000010004049620 x28-x30 = 0000000000aa55ff 000001001ef13d90 000001001ee66ba8 == Code context == 1001ee408fc: d5384240 mrs x0, currentel 1001ee40900: f100201f cmp x0, #0x8 1001ee40904: 54000040 b.eq 1001ee4090c <_start+0x10> // b.none 1001ee40908: d4000002 hvc #0x0 * 1001ee4090c: 94009d4f bl 1001ee67e48 <__bss_end__+0x17528> 1001ee40910: 14000000 b 1001ee40910 <_start+0x14> 1001ee40914: 00000000 udf #0 1001ee40918: 00000000 udf #0 1001ee4091c: 00000000 udf #0